STATUS_SEL=TXLEVEL
Execution/behavioural settings for state machine 0
| STATUS_N | Comparison level for the MOV x, STATUS instruction |
| STATUS_SEL | Comparison used for the MOV x, STATUS instruction. 0 (TXLEVEL): All-ones if TX FIFO level < N, otherwise all-zeroes 1 (RXLEVEL): All-ones if RX FIFO level < N, otherwise all-zeroes |
| WRAP_BOTTOM | After reaching wrap_top, execution is wrapped to this address. |
| WRAP_TOP | After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. |
| OUT_STICKY | Continuously assert the most recent OUT/SET to the pins |
| INLINE_OUT_EN | If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < …) |
| OUT_EN_SEL | Which data bit to use for inline OUT enable |
| JMP_PIN | The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. |
| SIDE_PINDIR | Side-set data is asserted to pin OEs instead of pin values |
| SIDE_EN | If 1, the delay MSB is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction. |
| EXEC_STALLED | An instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear once the instruction completes. |